NAND-type flash memory is known as an example of a conventional nonvolatile semiconductor memory device. A memory cell array in a NAND-type flash memory is configured having a plurality of NAND cell units arranged therein, each of the NAND cell units having a plurality of memory cells connected in series. One NAND cell unit includes a memory string configured from a plurality of memory cells connected in series and select gate transistors connected to the two ends of the memory string. The two ends of each of the NAND cell units are connected to a bit line and a source line. The control gates of the plurality of memory cells within the NAND cell unit are each connected to different word lines.
In NAND-type flash memory, the plurality of memory cells within one NAND cell unit are connected in series so as to share sources and drains. Moreover, the select gate transistors and their bit line contacts and source line contacts are shared by the plurality of memory cells in one NAND string. In addition, the shape of the element region of word lines or memory cells is close to a simple striped shape, hence making the NAND-type flash memory suited to miniaturization, and allowing a large capacity flash memory to be realized.
However, in the above-described NAND-type flash memory, the threshold voltage distribution indicating erase state gradually shifts in a negative direction thus giving rise to an over-erase state. When such an over-erase state occurs, there is an increase in stress on the memory cell itself that is subject to erase, thus hastening deterioration of the gate insulating film (sometimes referred to as tunnel insulating film) in the memory cell.